1. Field of the Invention
The present invention relates to differential-signal input and output circuits suited to improve the skew between a pair of differential signals, such as that in the Universal Serial Bus (USB), which transfers differential signals having opposite logic levels.
2. Description of the Related Art
To unify the standards of connectors provided for modules used with a personal computer, such as a display, a keyboard, or a mouse, the USB has been employed in these days. Between these modules and a personal computer, a series of packet data is transferred through the USB by using a pair of differential signals having opposite logic levels. Since data is transferred in serial in the USB, a few wires are required. The USB uses a cable having four wires for a pair of differential signal lines, a power line, and a ground line. Therefore, each module needs a connector having only a few pins, and in addition, the diameter of a cable connected to the connector is relatively small. In the USB, since data is transferred by a pair of differential signals, noise components having the same phase are eliminated. In the USB, to identify packet data, signals having logical xe2x80x9c0xe2x80x9d are inserted for a predetermined period between adjacent packet data.
FIG. 8 is a view showing the signal waveforms of the USB.
As shown in FIG. 8, it is required in the USB that a crossover voltage VCR, the voltage at the point where two differential signals having opposite logic levels intersect when one of them rises and the other falls, fall in a very narrow voltage zone (between VCRL and VCRH in the figure).
If a timing shift (hereinafter called a skew) is large between the differential signals, it is difficult for a module which receives the differential signals to obtain the correct packet data, and a transfer error of packet data may occur. To avoid this error, a differential-signal output circuit for reducing the skew of differential signals and for outputting them to the USB, or a receiver for reducing the skew of differential signals, generated during signal propagation are required.
FIG. 9 is a view of an example circuit for generating differential signals having a small skew. FIG. 10 is a view showing the operation waveforms of the circuit shown in FIG. 9.
The circuit shown in FIG. 9 includes an input terminal 113, an inverter 111 connected to the input terminal 113, an inverter 112 connected to the output side of the inverter 111, an output terminal 114 connected to the output side of the inverter 112, and an output terminal 115 connected to the connection point of the inverter 111 and the inverter 112.
A signal A shown in FIG. 10 is input to the inverter 111 through the input terminal 113. The inverter 111 inverts the input signal A in logic to generate a signal Bxe2x80x2 shown in FIG. 10. The generated signal Bxe2x80x2 is output to the outside through the output terminal 115 and is also input to the inverter 112. The inverter 112 inverts the input signal Bxe2x80x2 in logic to generate a signal Axe2x80x2. The generated signal Axe2x80x2 is output to the outside through the output terminal 114. In this way, differential signals Axe2x80x2 and Bxe2x80x2 having a small skew of only the delay time of the inverter 112 are output to the outside.
However, in the above circuit, a signal required to identify packet data, such as both signals Axe2x80x2 and Bxe2x80x2 having a logical xe2x80x9c0xe2x80x9d for a predetermined period, cannot be output to the outside although the differential signals having a small skew can be output.
Also, if a large skew occurs between a pair of differential signals due to signal transfer, data is recognized incorrectly. Therefore, a circuit for reducing a skew generated during signal propagation is demanded.
The present invention has been made in consideration of the above circumstances. Accordingly, it is an object of the present invention to provide a differential-signal input and output circuit for outputting differential signals having a small skew and for outputting signals both having logical xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d in addition to the differential signals. Another object of the present invention is to provide a differential-signal input and output circuit for reducing the skew of differential signals, generated during propagation.
One of the foregoing objects is achieved through the provision of a differential-signal input and output circuit for receiving a pair of differential signals at first and second input terminals, and for changing and outputting the pair of differential signals almost at the same time at timing when whichever changes last changes.
In this differential-signal input and output circuit, two differential signals are changed and output almost at the same time at timing when whichever changes last changes. Therefore, even when two differential signals having a relatively large skew are input, differential signals having a relatively small skew are output, and thus, the skew of the two input signals is reduced.
Another of the foregoing objects is achieved through the provision of a differential-signal input and output circuit including two transistor groups each formed of two p-channel transistors and two n-channel transistors connected in series in this order from a power to the ground; a first input terminal connected to the gate of a first p-channel transistor of the two p-channel transistors constituting a first transistor group and to the gate of a first n-channel transistor of the two n-channel transistors constituting the first transistor group; a first output terminal connected to a first connection point of a p-channel transistor closer to the ground of the two p-channel transistors constituting the first transistor group and an n-channel transistor closer to the power of the two n-channel transistors constituting the first transistor group; a second input terminal connected to the gate of a second p-channel transistor of the two p-channel transistors constituting a second transistor group and to the gate of a second n-channel transistor of the two n-channel transistors constituting the second transistor group; a second output terminal connected to a connection point of a p-channel transistor closer to the ground of the two p-channel transistors constituting the second transistor group and an n-channel transistor closer to the power of the two n-channel transistors constituting the second transistor group; a first inverter whose input side is connected to the second input terminal and whose output side is connected to both of the gate of a third p-channel transistor of the two p-channel transistors constituting the first transistor group, other than the first p-channel transistor, and the gate of a third n-channel transistor of the two n-channel transistors constituting the first transistor group, other than the first n-channel transistor; and a second inverter whose input side is connected to the first input terminal and whose output side is connected to both of the gate of a fourth p-channel transistor of the two p-channel transistors constituting the second transistor group, other than the second p-channel transistor, and the gate of a fourth n-channel transistor of the two n-channel transistors constituting the second transistor group, other than the second n-channel transistor.
In this differential-signal input and output circuit, when two signals having opposite logic levels are input to the first and second input terminals, signals having the opposite logic levels obtained by inverting those of the input signals are output from the first and second output terminals. When two signals having the same logic level are input to the first and second input terminals, the first and second output terminals show a high-impedance state.
The differential-signal input and output circuit may be configured such that it further includes a first latch whose input side is connected to the first output terminal and a second latch whose input side is connected to the second output terminal; and the output point of the first latch serves as the first output terminal, and the output point of the second latch serves as the second output terminal.
In this case, the logical states of the first and second output terminals are maintained at the first and second latches. Therefore, even when the first and second output terminals show the high-impedance states, stable logic signals are output.
One of the foregoing objects is achieved in still another aspect of the present invention through the provision of a differential-signal input and output circuit for receiving two differential signals having opposite logic levels at first and second input terminals, wherein the differential-signal input and output circuit changes and outputs the two differential signals almost at the same time at timing when whichever changes last changes when the skew between the two differential signals is less than a delay period specified by a delay circuit, and the differential-signal input and output circuit operates as just a buffer when the skew between the two differential signals is equal to or more than the delay period specified by the delay circuit.
In this differential-signal input and output circuit, differential signals having a small skew are output, and signals both having logical xe2x80x9c0xe2x80x9d or logical xe2x80x9c1xe2x80x9d can be output, other than differential signals.
One of the foregoing objects is achieved in yet another aspect of the present invention through the provision of a differential-signal input and output circuit including four transistor groups each formed of two p-channel transistors and two n-channel transistors connected in series in this order from a power to the ground; a first input terminal connected to all of the gate of a first p-channel transistor of the two p-channel transistors constituting a first transistor group among the four transistor groups, the gate of a first n-channel transistor of the two n-channel transistors constituting the first transistor group, the gate of a second p-channel transistor of the two p-channel transistors constituting a second transistor group among the four transistor groups, and the gate of a second n-channel transistor of the two n-channel transistors constituting the second transistor group; a first output terminal connected to both of a first connection point of a p-channel transistor closer to the ground of the two p-channel transistors constituting the first transistor group and an n-channel transistor closer to the power of the two n-channel transistors constituting the first transistor group, and a second connection point of a p-channel transistor closer to the ground of the two p-channel transistors constituting the second transistor group and an n-channel transistor closer to the power of the two n-channel transistors constituting the second transistor group; a second input terminal connected to all of the gate of a third p-channel transistor of the two p-channel transistors constituting a third transistor group among the four transistor groups, the gate of a third n-channel transistor of the two n-channel transistors constituting the third transistor group, the gate of a fourth p-channel transistor of the two p-channel transistors constituting a fourth transistor group among the four transistor groups, and the gate of a fourth n-channel transistor of the two n-channel transistors constituting the fourth transistor group; a second output terminal connected to both of a third connection point of a p-channel transistor closer to the ground of the two p-channel transistors constituting the third transistor group and an n-channel transistor closer to the power of the two n-channel transistors constituting the third transistor group, and a fourth connection point of a p-channel transistor closer to the ground of the two p-channel transistors constituting the fourth transistor group and an n-channel transistor closer to the power of the two n-channel transistors constituting the fourth transistor group; a first inverter whose input side is connected to the second input terminal and whose output side is connected to both of the gate of a fifth p-channel transistor of the two p-channel transistors constituting the first transistor group, other than the first p-channel transistor, and the gate of a fifth n-channel transistor of the two n-channel transistors constituting the first transistor group, other than the first n-channel transistor; a first delay circuit whose input side is connected to the first input terminal and whose output side is connected to both of the gate of a sixth p-channel transistor of the two p-channel transistors constituting the second transistor group, other than the second p-channel transistor, and the gate of a sixth n-channel transistor of the two n-channel transistors constituting the second transistor group, other than the second n-channel transistor; a second inverter whose input side is connected to the first input terminal and whose output side is connected to both of the gate of a seventh p-channel transistor of the two p-channel transistors constituting the third transistor group, other than the third p-channel transistor, and the gate of a seventh n-channel transistor of the two n-channel transistors constituting the third transistor group, other than the third n-channel transistor; and a second delay circuit whose input side is connected to the second input terminal and whose output side is connected to both of the gate of an eighth p-channel transistor of the two p-channel transistors constituting the fourth transistor group, other than the fourth p-channel transistor, and the gate of an eighth n-channel transistor of the two n-channel transistors constituting the fourth transistor group, other than the fourth n-channel transistor.
In this differential-signal input and output circuit, two signals having opposite logic levels are input to the first and second input terminals. When the skew of the two input signals are less than the delay period of the first and second delay circuits, since the two signals are changed and output at the same time at timing when whichever of the two signals changes last changes, differential signals having a small skew are output. When the skew of the two input signals is equal to or more than the delay period of the first and second delay circuits, the input signals are output as they are. Therefore, the skew of differential signals is reduced, and signals, such as those having logical xe2x80x9c0xe2x80x9d for a predetermined period, required to identify packet data, are obtained.
It is preferred that a first latch whose input side is connected to both of the first connection point and the second connection point and a second latch whose input side is connected to both of the third connection point and the fourth connection point be provided, the first output terminal be connected to the output side of the first latch instead of to the first and second connection points, and the second output terminal be connected to the output side of the second latch instead of to the third and fourth connection points.
In this case, because the logical state of the first and second connection points is maintained by the first latch, and the logical state of the third and fourth connection points is maintained by the second latch, even when the first and second connection points or the third and fourth connection points show the high-impedance state, the logical states of the first and second output terminals are stable.